Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs

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dc.contributor.authorSoltaniyeh, Mohammadreza
dc.contributor.authorKadayif, Ismail
dc.contributor.authorOzturk, Ozcan
dc.date.accessioned2025-01-27T20:45:59Z
dc.date.available2025-01-27T20:45:59Z
dc.date.issued2018
dc.departmentÇanakkale Onsekiz Mart Üniversitesi
dc.description.abstractAs shown in some prior studies, a significant percentage of data blocks accessed in parallel codes are private, and not keeping track of those blocks can improve the effectiveness of directory structures in Chip multiprocessors (CMPs). In this paper, we have two major contributions. First, we showed that compared to the classification of cache blocks at page granularity, data block classification (DBC) at subpage level helps to detect considerably more private data blocks. Based on this idea, we propose two different approaches for enhancing the effectiveness of directory caches in tiled CMPs. In the first approach, which is called quasi-dynamic subpage level DBC (QDBC), a data block is assumed to be private from the beginning of the program execution and stays private as long as the corresponding subpage is accessed by only one core. Our second approach, which is called dynamic subpage level DBC, turns a data block into private again after all blocks within the corresponding subpage are evicted from private cache hierarchy. Memory block classification at subpage level, however, may increase the frequency of the operating system involvement in updating the maintenance bits in page table entries. To overcome this, we propose, as a second contribution, a distributed table called as on-chip page table (o-CPT), which stores recently accessed page translations in the system. Our simulation results show that, compared to page level data classification, QDBC and DBC approaches relying on the o-CPT can detect significantly more private data blocks and considerably improve system performance.
dc.description.sponsorshipScientific and Technological Research Council of Turkey [113E258]
dc.description.sponsorshipThis work was supported by the Scientific and Technological Research Council of Turkey under Grant 113E258.
dc.identifier.doi10.1109/TCAD.2017.2729280
dc.identifier.endpage819
dc.identifier.issn0278-0070
dc.identifier.issn1937-4151
dc.identifier.issue4
dc.identifier.scopus2-s2.0-85028805190
dc.identifier.scopusqualityQ1
dc.identifier.startpage806
dc.identifier.urihttps://doi.org/10.1109/TCAD.2017.2729280
dc.identifier.urihttps://hdl.handle.net/20.500.12428/24779
dc.identifier.volume37
dc.identifier.wosWOS:000427850100008
dc.identifier.wosqualityQ2
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc
dc.relation.ispartofIeee Transactions on Computer-Aided Design of Integrated Circuits and Systems
dc.relation.publicationcategoryinfo:eu-repo/semantics/openAccess
dc.rightsinfo:eu-repo/semantics/openAccess
dc.snmzKA_WoS_20250125
dc.subjectAddress translation
dc.subjectcache coherence
dc.subjectchip multiprocessor (CMP)
dc.subjectdirectory cache
dc.subjectpage table
dc.subjecttranslation look-aside buffer (TLB)
dc.titleClassifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs
dc.typeArticle

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