Capturing and optimizing the interactions between prefetching and cache line turnoff

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dc.contributor.authorKadayif, Ismail
dc.contributor.authorZorlubas, Ayhan
dc.contributor.authorKoyuncu, Selcuk
dc.contributor.authorKabal, Olcay
dc.contributor.authorAkcicek, Davut
dc.contributor.authorSahin, Yucel
dc.contributor.authorKandemir, Mahmut
dc.date.accessioned2025-01-27T21:13:08Z
dc.date.available2025-01-27T21:13:08Z
dc.date.issued2008
dc.departmentÇanakkale Onsekiz Mart Üniversitesi
dc.description.abstractWhile numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance oriented techniques influence energy behavior of the cache, and the energy oriented techniques Usually increase program execution cycles. The overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. This paper first studies this interaction and demonstrates how performance and energy optimizations can affect each other. We then propose three optimization schemes that turn-off cache lines in a prefetching-sensitive manner. Specifically, these schemes treat prefetched cache lines differently from the lines brought to the cache in a normal way (i.e., through a load operation) in turning off the cache lines. Our experiments with five randomly selected codes from the SPEC2000 suite indicate that the proposed approaches save significant leakage energy. Our results also show that the performance degradations incurred by the proposed approaches are very small. (c) 2008 Elsevier B.V. All rights reserved.
dc.identifier.doi10.1016/j.micpro.2008.05.003
dc.identifier.endpage404
dc.identifier.issn0141-9331
dc.identifier.issn1872-9436
dc.identifier.issue7
dc.identifier.scopus2-s2.0-54549086766
dc.identifier.scopusqualityQ1
dc.identifier.startpage394
dc.identifier.urihttps://doi.org/10.1016/j.micpro.2008.05.003
dc.identifier.urihttps://hdl.handle.net/20.500.12428/28302
dc.identifier.volume32
dc.identifier.wosWOS:000260692100005
dc.identifier.wosqualityQ3
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherElsevier
dc.relation.ispartofMicroprocessors and Microsystems
dc.relation.publicationcategoryinfo:eu-repo/semantics/openAccess
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_WoS_20250125
dc.subjectEmbedded system design
dc.subjectCache line turnoff
dc.subjectPrefetching
dc.subjectLeakage
dc.titleCapturing and optimizing the interactions between prefetching and cache line turnoff
dc.typeArticle

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