Reducing performance impact of process variation for data caches

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dc.contributor.authorKadayif, Ismail
dc.contributor.authorTuncer, Kadir
dc.date.accessioned2025-01-27T18:53:03Z
dc.date.available2025-01-27T18:53:03Z
dc.date.issued2013
dc.departmentÇanakkale Onsekiz Mart Üniversitesi
dc.description8th International Conference on Electrical and Electronics Engineering, ELECO 2013 -- 28 November 2013 through 30 November 2013 -- Bursa -- 102644
dc.description.abstractIn concurrent with finer-granular process technologies, it is becoming extremely difficult to keep critical physical device parameters within desired bounds, including channel length, gate oxide thickness, and dopant ion concentration. Variations in these parameters can lead to dramatic variations in access latencies in Static Random Access Memory (SRAM) devices: Different lines of the same cache may have different access latencies. A simple solution to this problem is to adopt the worst-case latency paradigm. While this egalitarian cache management is simple, it may introduce significant performance overhead for data cache accesses. To overcome varying access latencies across different data cache lines, we employ a small table storing the access latencies of cache lines. This table is accessed during data cache access to give a hint to the hardware about how long to wait for data to become available. © 2013 The Chamber of Turkish Electrical Engineers-Bursa.
dc.identifier.doi10.1109/eleco.2013.6713866
dc.identifier.endpage384
dc.identifier.isbn978-605010504-9
dc.identifier.scopus2-s2.0-84894158932
dc.identifier.scopusqualityN/A
dc.identifier.startpage380
dc.identifier.urihttps://doi.org/10.1109/eleco.2013.6713866
dc.identifier.urihttps://hdl.handle.net/20.500.12428/12562
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIEEE Computer Society
dc.relation.ispartofELECO 2013 - 8th International Conference on Electrical and Electronics Engineering
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_Scopus_20250125
dc.subjectStatic random access storage; Gate oxide thickness; Ion concentrations; Performance impact; Physical devices; Process Technologies; Process Variation; Static random access memory; Worst-case latencies; Cache memory
dc.titleReducing performance impact of process variation for data caches
dc.typeConference Object

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