Reducing data TLB power via compiler-directed address generation

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dc.contributor.authorKadayif, Ismail
dc.contributor.authorNath, Partho
dc.contributor.authorKandemir, Mahmut
dc.contributor.authorSivasubramaniam, Anand
dc.date.accessioned2025-01-27T20:59:36Z
dc.date.available2025-01-27T20:59:36Z
dc.date.issued2007
dc.departmentÇanakkale Onsekiz Mart Üniversitesi
dc.description.abstractAddress translation using the translation lookaside buffer (TLB) consumes as much as 16 % of the chip power on some processors because of its high associativity and access frequency. While prior work has looked into optimizing this structure at the circuit and architectural levels, this paper takes a different approach to optimizing its power by reducing the number of data TLB (dTLB) lookups for data references. The main idea is to keep translations in a set of translation registers (TRs) and intelligently use them in software to directly generate the physical addresses without going through the dTLB. The software has to work within the confines of the TRs provided by the hardware and has to maximize the reuse of such translations to be effective. The authors propose strategies and code transformations for achieving this in array-based and pointer-based codes, looking to optimize data accesses. Results with a suite of Spec95 array-based and pointer-based codes show dTLB energy savings of up to 73% and 88%, respectively, compared to directly using the dTLB for all references. Despite the small increase in instructions executed with the mechanisms, the approach can, in fact, provide performance benefits in certain cache-addressing strategies.
dc.identifier.doi10.1109/TCAD.2006.882599
dc.identifier.endpage324
dc.identifier.issn0278-0070
dc.identifier.issn1937-4151
dc.identifier.issue2
dc.identifier.scopus2-s2.0-33846644931
dc.identifier.scopusqualityQ1
dc.identifier.startpage312
dc.identifier.urihttps://doi.org/10.1109/TCAD.2006.882599
dc.identifier.urihttps://hdl.handle.net/20.500.12428/26741
dc.identifier.volume26
dc.identifier.wosWOS:000243953000012
dc.identifier.wosqualityQ2
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc
dc.relation.ispartofIeee Transactions on Computer-Aided Design of Integrated Circuits and Systems
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_WoS_20250125
dc.subjectaddress translation
dc.subjectcompiler optimizations
dc.subjectembedded systems design
dc.subjectlow power
dc.subjecttranslation lookaside buffers (TLBs)
dc.titleReducing data TLB power via compiler-directed address generation
dc.typeArticle

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