Modeling and Improving Data Cache Reliability

Soft errors arising front energetic particle strikes pose a significant reliability concern for computing systems, especially for those running in noisy environments. Technology scaling and aggressive leakage control mechanisms make: the problem caused by these transient errors even snore severe. Therefore, it is very important to employ reliability enhancing mechanisms in processor/memory designs to protect them against soft errors. To do so, we first need to model soft errors, and their study cost/reliability tradeoffs among various reliability enhancing techniques based on tire model so that system requireirients could be met. Since cache memories take the largest fraction of on-chip real estate today and their share is expected to continue to grow in future designs, they are more vulnerable to soft errors, as compared to many other components of a, computing system. In this paper, we first focus on a soft error model for L1 data caches, and then explore different reliability enhancing mechanisms. More specifically, we define a, metric called AVFC (Architectural Vulnerability factor for Caches), which represents tire probability with which a fault in the cache can be visible in the final output of the program. Based on this model, we then propose three architectural schemes for improving reliability in tire existence of soft errors. Our first scheme prevents air error from propagating to the lower levels in the memory hierarchy by riot forwarding tire unmodified data words of a dirty cache block to the L2 cache when the dirty block is to be replaced. The second scheme proposed selectively invalidates cache blocks to reduce their vulnerable periods, decreasing their chances of catching any soft errors. Based on the AVFC metric, our experimental results show that these two schemes are very effective in alleviating soft; errors in the L1 data cache. Specifically; by rising our first scheme; it is possible to improve the AVFC metric by 32% without any performance loss. Oft the other hand, tire second scheme enhances the AVFC metric between 60% and 97%, at the cost of a. performance degradation which varies from 0% to 21.3%, depending on how aggressively the cache blocks are invalidated. To reduce the performance overhead caused by cache block invalidation, we also propose a third scheme which tries to bring a fresh copy of tire invalidated block into tire cache via prefetching. Our experimental results indicate that, this scheme can reduce the performance overheads to less than 1% for all applications in our experimental suite, at the cost of giving tip a tolerable portion of tire reliability enhancement the second scheme achieves.