Reducing Performance Impact of Process Variation For Data Caches
| dc.contributor.author | Kadayif, Ismail | |
| dc.contributor.author | Tuncer, Kadir | |
| dc.date.accessioned | 2025-01-27T21:07:23Z | |
| dc.date.available | 2025-01-27T21:07:23Z | |
| dc.date.issued | 2013 | |
| dc.department | Çanakkale Onsekiz Mart Üniversitesi | |
| dc.description | 8th International Conference on Electrical and Electronics Engineering (ELECO) -- NOV 28-30, 2013 -- Bursa, TURKEY | |
| dc.description.abstract | In concurrent with finer-granular process technologies, it is becoming extremely difficult to keep critical physical device parameters within desired bounds, including channel length, gate oxide thickness, and dopant ion concentration. Variations in these parameters can lead to dramatic variations in access latencies in Static Random Access Memory (SRAM) devices: Different lines of the same cache may have different access latencies. A simple solution to this problem is to adopt the worst-case latency paradigm. While this egalitarian cache management is simple, it may introduce significant performance overhead for data cache accesses. To overcome varying access latencies across different data cache lines, we employ a small table storing the access latencies of cache lines. This table is accessed during data cache access to give a hint to the hardware about how long to wait for data to become available. | |
| dc.description.sponsorship | Chamber Elect Engineers Bursa Branch,Istanbul Techn Univ, Fac Elect & Elect Engn,Uludag Univ, Dept Elect & Elect Engn,IEEE, Reg 8,IEEE Turkey Sect, CAS Chapter,Sci & Technol Res Council Turkey | |
| dc.identifier.endpage | 384 | |
| dc.identifier.isbn | 978-605-01-0504-9 | |
| dc.identifier.startpage | 380 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12428/28033 | |
| dc.identifier.wos | WOS:000333752200080 | |
| dc.identifier.wosquality | N/A | |
| dc.indekslendigikaynak | Web of Science | |
| dc.language.iso | en | |
| dc.publisher | IEEE | |
| dc.relation.ispartof | 2013 8th International Conference on Electrical and Electronics Engineering (Eleco) | |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | |
| dc.rights | info:eu-repo/semantics/closedAccess | |
| dc.snmz | KA_WoS_20250125 | |
| dc.title | Reducing Performance Impact of Process Variation For Data Caches | |
| dc.type | Conference Object |
